SITE
What It Is
The site is the parcel of land, the foundation, the building envelope, the cleanroom shell, and the utility interconnections that must exist before a single tool is installed. A leading-edge fab is among the largest and most expensive buildings ever constructed. Intel's Ohio One campus spans 2.5 million square feet including 600,000 square feet of cleanroom production space. Samsung's Taylor complex sits on 1,200 acres of former farmland in Williamson County, Texas, with approximately 4 million square feet already constructed including a six-story office building. TSMC's Arizona campus is on track to become a "gigafab cluster" with $65 billion committed to three fabs and an additional $100 billion pledged for future expansion, making it the largest foreign direct investment in a greenfield project in U.S. history.
A single advanced fab (sub-4nm node) costs $10-20 billion or more. Intel's two Ohio fabs are budgeted at roughly $28 billion. Samsung's Taylor investment has expanded from an initial $17 billion to an estimated $44 billion with the addition of a second advanced fab and expanded R&D. TSMC's three Phoenix fabs total $65 billion. The CHIPS Act has driven over $540 billion in announced investments across 28+ U.S. states, transforming Arizona, Texas, and Ohio into the primary nodes of American semiconductor construction.
Building fabs in the U.S. is estimated to be 30-50% more expensive than in Asia. Arizona and Texas represent mature ecosystems with existing semiconductor supply chains; Ohio represents a "build it and they will come" approach. The construction timelines are sobering: TSMC CEO C.C. Wei noted that establishing the Arizona plant has taken "twice as long as similar facilities in Taiwan." Intel's Ohio project, originally slated for 2026 operation, has been pushed to 2030-2031. Samsung's Taylor fab, announced in 2021 for 2024 operation, is now targeting partial operation by late 2026 with full production by 2028.
Why It Matters
Site selection is the first irreversible decision. You cannot relocate a fab. The building must survive decades, accommodate technology transitions, and connect to utility infrastructure that takes 10-20 years to fully ramp. The electric, water, and wastewater requirements can rival that of a moderately-sized town, and the rise of more comprehensive ESG compliance standards is now a factor in siting decisions.
What Constrains It
- Cost premium: 30-50% more expensive to build in the U.S. vs. Asia
- Utility infrastructure: 10-20 year ramp-up for electric, water, wastewater, gas delivery
- Talent availability: Each fab requires thousands of specialized workers; Intel has 162 Ohio employees as of early 2025
- Construction timeline: U.S. projects consistently delayed 2-4 years vs. Asian equivalents
- Ecosystem maturity: Ohio lacks the dense supplier network of Phoenix or Austin
Connects To
Utilities (power and water contracts are negotiated before ground breaks); Subfab & Vacuum (foundation must accommodate raised floors creating 1-3 meter plenum); Tools (building vibration specs determine lithography placement); Environmental (ESG requirements affect siting).
UTILITIES
What It Is
The utility systems that keep a fab alive: electricity, ultrapure water, process chemicals and gases, cleanroom air, and wastewater treatment. A single 12-inch wafer fab consumes 100-200 MW of continuous power, equivalent to a small city. TSMC's Arizona Phase 1 will consume roughly 200 MW; the planned expansion could grow to over 1 GW, roughly equivalent to a new nuclear reactor. The semiconductor industry accounts for approximately 1% of global electricity consumption, expected to double by 2030. Global semiconductor manufacturing is projected to consume 237 TWh by 2030, on par with all of Australia's electricity consumption.
Power specifics: Energy consumption ranges from 100-150 kWh per square centimeter of wafer produced. In 2024, TSMC's total energy consumption was 27,456 GWh, with purchased electricity accounting for approximately 93%. TSMC implemented 1,177 energy conservation measures achieving a 15% energy-saving rate and conserving 810 GWh. TSMC has cumulatively signed contracts for 4.4 GW of renewable energy procurement, estimated to reduce carbon emissions by approximately 5.23 million metric tons annually. Starting in 2025, TSMC is expected to receive electricity from offshore wind power. TSMC is projected to use 12.5% of Taiwan's entire electricity supply by 2025.
Water specifics: Semiconductor fabs consume 2-4 million gallons of municipal water daily. Advanced fabs use 4.5-7 liters per cm² of processed wafer. A single fab uses roughly 20-38 million liters of water per day, enough to rival the daily consumption of a small city. TSMC consumed 101 billion liters of water in 2023 alone. Water recycling rates average 65-75% across semiconductor facilities, with industry targets of 85-90% for next-generation fabs. Some closed-loop systems achieve 85-92% water reuse. UPW must achieve resistivity exceeding 18.2 MΩ·cm at 25°C, with TOC below 1 ppb, particle counts under 1 particle/mL (>0.05 µm), and bacteria below 0.1 CFU/mL. A single 200mm wafer requires 5,600 liters of ultrapure water for cleaning processes. UPW production consumes 3-7 kWh per 1,000 gallons, with 20-25% of raw water lost during purification.
Cleanroom air: Most semiconductor wafer fabrication occurs in ISO 14644-1 Class 4-6 cleanrooms (352-35,200 particles/m³ at 0.5 µm). The most critical process areas (photolithography, etching) demand ISO Class 3, only 10 particles ≥0.1 µm per cubic meter. Some leading-edge processes now require ISO Class 1-2, with ISO 1 allowing less than 2 particles >0.3 µm per cubic meter and requiring 500-750 air changes per hour with 100% ULPA filtration. ULPA filters are 99.9995% efficient at capturing particles down to 0.12 µm. A single dust particle measuring 0.5 microns can be a catastrophic "boulder" on a 5-nanometer circuit path.
Why It Matters
Utilities are the binding constraint on expansion. Power availability determines whether a fab can operate at all. Water scarcity in Arizona, Texas, and Taiwan is already a limiting factor. Intel conserved approximately 10.2 billion gallons of water in 2023 and enabled restoration of 3.1 billion gallons through watershed projects, maintaining net positive water in the U.S. and India. Samsung's Taylor fab will use primarily groundwater supplied by Epcor for industrial water.
What Constrains It
- Grid capacity: 1 GW+ demand per gigafab requires transmission system expansion; Arizona Public Service faces this challenge now
- Water scarcity: Fabs expanding in drought-prone regions compete with agriculture and municipalities
- Cleanroom energy: 500-750 air changes per hour consume enormous energy; airflow optimization is an active engineering discipline
- UPW purity: Advanced nodes at 3nm and 2nm demand TOC below 0.5 ppb, stricter than earlier generations
Connects To
Site (utility contracts negotiated pre-construction); Subfab & Vacuum (vacuum pumps and abatement consume significant utility load); Environmental (energy and water are the two largest environmental footprints); Tools (cleanroom classification determines tool placement and mini-environment requirements).
Related readingSee how utilities feed the machine beneath the cleanroom.
TOOLS: LITHOGRAPHY
What It Is
Lithography is the optical engine of the semiconductor industry. It prints the circuit patterns onto wafers using light of progressively shorter wavelengths. ASML is the sole supplier of EUV (extreme ultraviolet) lithography equipment, a monopoly with no serious challenger.
The ASML TwinScan EXE:5200 (second-generation High-NA EUV) will ship first modules to Intel in 2025, with volume production targeted for 2026. The EXE:5200 achieves higher wafer throughput than the EXE:5000, exceeding 185 wafers per hour, while supporting advanced sub-2nm processes. Three EXE:5000 units were delivered for R&D to Intel and TSMC. Intel is first to receive the EXE:5200 for its 14A node; TSMC may begin high-NA mass production in 2028.
Each High-NA EUV scanner costs over $400 million. Intel purchased two of these tools in Q4 2024 alone. A single EUV scanner requires approximately 1 MW of power to operate. ASML's 2025 sales forecast is 30-35 billion euros; the U.S. was ASML's largest market in Q4 2024 at 28% of sales.
Future EUV scanners will move to a common platform for NXE, EXE, and future hyper-NA systems. Hyper-NA EUV machines with 0.75 numerical aperture are under consideration for potential deployment around 2032. A potential transition to 6x12" masks (from the 6x6" standard since the 1980s) is being discussed, equivalent in significance to the move from 200mm to 300mm wafers.
Why It Matters
Lithography is the single most expensive and most concentrated point in the entire semiconductor supply chain. When ASML has a production delay, the entire industry's roadmap slips. The transition to High-NA EUV is a generational inflection point: Intel is betting its 14A node on being first to High-NA, while TSMC has the commercial leverage to wait until yield economics justify the $400M+ per tool investment. Intel itself has acknowledged that 14A is feasible without High-NA, the advantage on most layers is "design flexibility and process simplification, tangential to cost."
What Constrains It
- ASML monopoly: No alternative EUV supplier exists; geopolitical access to ASML tools is a strategic flashpoint
- Cost: $400M+ per High-NA tool concentrates investment among fewer players
- Power: Each scanner draws ~1 MW; a fab with 10+ EUV tools needs dedicated power infrastructure
- Timeline: Intel 14A (2026) vs. TSMC (2028?) vs. Samsung, first-mover advantage is contested
- Mask transition: Potential shift to 6x12" masks would reshape the entire reticle supply chain
Connects To
Metrology (every printed layer must be measured for CD and overlay); Deposition & Etch (pattern transfer follows lithography); Utilities (power and cleanroom classification are lithography-driven); Exit (lithography defectivity determines yield before test).
TOOLS: DEPOSITION & ETCH
What It Is
After lithography prints a pattern, deposition adds material and etch removes it. These processes repeat hundreds of times per wafer, building transistors and interconnects one atomic layer at a time.
Deposition: The global semiconductor deposition equipment market is valued at $41.2 billion in 2025, projected to reach $68.5 billion by 2033 at 7.8% CAGR. The market segments by technology:
- CVD (Chemical Vapor Deposition): 38.2% market share, high-throughput dielectric and metal deposition at 600-800°C
- ALD (Atomic Layer Deposition): 22.1% market share, sub-nanometer thickness control via sequential self-limiting reactions at 200-400°C; fastest-growing segment at 9.8% CAGR
- PVD (Physical Vapor Deposition): 18.4% market share, magnetron sputtering for interconnect metals in ultra-high vacuum; slowest growth at 5.2% CAGR
- Epitaxy: 14.2% market share, silicon epitaxy for logic device source-drain engineering at 500-900°C; growing at 8.6% CAGR
Key suppliers: Applied Materials, Lam Research, Tokyo Electron, and ASM International. "The shift toward chiplet architectures and heterogeneous integration demands new deposition capabilities for advanced packaging and interconnect layers."
Etch: Etching comes in multiple forms. Wet chemical etching uses liquid-based chemistries for precise but slower processing. Plasma/RIE (Reactive Ion Etching) dry etching uses reactive ionized gases for high-precision anisotropic pattern transfer, the dominant method for advanced nodes. Deep RIE (the Bosch process) enables MEMS and TSV fabrication with extremely high aspect ratios. The RIE mechanism involves synergistic chemical reaction and physical sputtering, "the bombardment catalyzes the surface chemical reactions." PFAS-containing wet chemistries are critical for semiconductor wet processing, used in wet chemical etching, planarization, electroplating, and wafer cleaning.
CMP (Chemical Mechanical Planarization): CMP is the dominant planarization technique, using aqueous chemical slurry with abrasive particles and a pad providing contact pressure. It serves as the critical step that flattens each deposited layer before the next lithography step.
Why It Matters
Deposition and etch are where the transistor actually gets built. Lithography prints the blueprint; deposition and etch construct the building. Every process node shrink requires new deposition chemistries and more precise etch control. The shift to 3D architectures (GAA transistors, 3D NAND with 200+ layers) dramatically increases the number of deposition and etch steps per wafer, directly multiplying tool count, process time, and cost.
What Constrains It
- Equipment concentration: Applied Materials, Lam Research, Tokyo Electron, and ASM International dominate; limited second sources
- PFAS dependency: Wet chemistries critical for etching face increasing environmental regulation
- Process complexity: Sub-2nm nodes require atomic-scale control; any deviation across hundreds of steps compounds into yield loss
- RIE damage: "The RIE process involves high-energy ion bombardment on the surface of the wafer. This can be extremely dangerous for the device itself and can lead to failure and reliability problems."
Connects To
Lithography (deposition/etch follow every lithography step); Metrology (each step requires dimensional and defect measurement); Subfab & Vacuum (deposition and etch tools are the largest consumers of vacuum and gas delivery); Environmental (PFAS chemistries and etch byproducts are major emissions sources).
TOOLS: METROLOGY
What It Is
Metrology is the measurement science that verifies every step of the manufacturing process. You cannot manufacture what you cannot measure. CD-SEMs (Critical Dimension Scanning Electron Microscopes) are optimized for IC manufacturing with low-electron landing energy (300-800 eV), capable of measuring 7nm feature size FinFET and nanowire devices, extendable to sub-5nm with simulation.
Key metrology tool categories include: dimensional metrology (CD-SEM), optical metrology (ellipsometry, OCD), electron microscopy (SEM/TEM), X-ray metrology (XRD/XRF), and electrical metrology. Overlay metrology ensures layer alignment with sub-nanometer accuracy. Defect inspection uses automated optical and electron-beam inspection at massive throughput.
Leading suppliers include Onto Innovation, which provides: Aspect IR CD for 3D NAND/DRAM, Atlas III+ for OCD/thin film measurement, IMPULSE+ for CMP process control, and FAaST systems for non-contact electrical metrology. "Scanning electron microscopy is one of the most versatile techniques used for in-line IC measurements... Specialized critical dimension SEMs are optimized for IC manufacturing."
The industry is moving toward hybrid metrology, combining multiple techniques to obtain information on parts of features that cannot be measured directly. High-throughput solutions like automated optical inspection (AOI) ensure fast, reliable measurements at production scale.
Why It Matters
Metrology is not quality control, it is process control. Every deposition, etch, and lithography step is verified before the next step begins. At 3nm, a single nanometer of overlay misalignment can destroy device performance. Metrology tools operate at the physical limits of measurement: sub-nanometer precision on features smaller than a virus, at throughput rates of thousands of wafers per day.
What Constrains It
- Resolution vs. throughput tradeoff: Electron-beam metrology has higher resolution but is slower than optical; hybrid approaches add complexity
- 3D measurement challenge: As devices go vertical (3D NAND, GAA), measuring internal structures requires new techniques like X-ray and IR-based methods
- Tool cost and footprint: Metrology tools occupy significant cleanroom space and represent a meaningful portion of total fab CapEx
- Data volume: Advanced fabs generate petabytes of metrology data; analysis infrastructure is a growing constraint
Connects To
Lithography (overlay and CD control feedback loops); Deposition & Etch (film thickness and etch depth verification); Exit (metrology data feeds yield analysis and binning decisions); Movement (AMHS must route wafers to metrology stations between process steps).
SUBFAB & VACUUM
What It Is
The sub-fab is the invisible half of the fab. It houses pumps, power supplies, gas lines, abatement systems, and other support equipment below the cleanroom floor, keeping heat, vibration, and maintenance out of the pristine "ballroom" above. Significant energy is consumed in the sub-fab for removal and treatment of process gases and liquids, thermal management (both heating and cooling). The balance between emissions reduction and energy consumption for abatement must be carefully managed.
Vacuum systems are the heart of the sub-fab. The global semiconductor dry vacuum pump market was valued at approximately $1.59 billion in 2025, projected to reach $3.39 billion by 2034 at 8.8% CAGR. Over 870,000 dry vacuum pumps are currently in use globally, with demand driven by sub-5nm nodes and 3D NAND architectures.
Major suppliers:
- Edwards Vacuum (Atlas Copco): Dominant in dry vacuum and abatement systems, with products including iXH dry pumps, STP turbomolecular pumps, and CTI-Cryogenics cryopumps. Opened a new Arizona factory to supply 120,000+ units annually.
- Ebara Corporation: Critical for dry vacuum pumps and turbomolecular systems, with EV-S series dry pumps and A70 turbomolecular pumps. Signed joint development with TSMC for sub-3nm etch-process pumps. Their plasma-resistant dry pump achieved 36,000+ hours MTBF and is in service in 70+ advanced fabs.
- Pfeiffer Vacuum (Busch Group): Major vacuum supplier with growing semiconductor focus
- ULVAC and Osaka Vacuum: Japanese suppliers with significant market presence
Vacuum systems account for a significant share of fab utility load, driving manufacturers toward energy-efficient and smart monitoring solutions. Smart, IoT-enabled pumps with predictive maintenance are reducing intervention by 30%.
Why It Matters
The sub-fab is where the cleanroom meets reality. Every process tool in the ballroom above requires vacuum, power, cooling water, and gas connections routed through the sub-fab. A lithography scanner's vibration isolation, an etch chamber's vacuum level, and a CVD tool's gas purity all depend on sub-fab infrastructure. As process complexity increases, sub-fab infrastructure consumes more energy, and integration between sub-fab and cleanroom systems increasingly determines overall fab efficiency.
What Constrains It
- Supply concentration: Three players (Edwards, Ebara, Pfeiffer) dominate high-end vacuum; China's domestic suppliers face long qualification cycles
- Energy load: Sub-fab systems are major electricity consumers; efficiency improvements directly affect fab operating cost
- Predictive maintenance: 870,000+ pumps globally require service; smart monitoring is transitioning from luxury to necessity
- Abatement tradeoff: More aggressive emissions treatment consumes more energy; optimization is complex
Connects To
Utilities (sub-fab consumes power, cooling water, and gas); Deposition & Etch (vacuum quality directly affects film quality and etch profile); Environmental (abatement systems manage chemical emissions); Site (foundation design must accommodate raised floors and sub-fab access).
Related readingFollow the subfab as part of the integrated fab machine.
ENVIRONMENTAL
What It Is
The environmental subsystem encompasses water management, energy sourcing, emissions abatement, chemical safety, and the regulatory landscape that increasingly determines where and how fabs operate. Environmental is no longer a corporate communications exercise, it is a capacity planning variable.
Water: TSMC consumed 101 billion liters of water in 2023. A single fab uses 20-38 million liters per day. Water recycling rates are climbing: from 65-75% industry average to 85-92% for advanced closed-loop systems. Intel achieved net positive water in the U.S. and India by conserving 10.2 billion gallons and restoring 3.1 billion gallons through watershed projects in 2023. Samsung's Taylor fab will draw primarily from groundwater supplied by Epcor, not municipal supply, a decision that raises questions about aquifer sustainability in Central Texas.
Energy and emissions: The semiconductor industry accounts for ~1% of global electricity consumption, projected to double by 2030. Global manufacturing will consume 237 TWh by 2030, equivalent to Australia's total electricity use. TSMC is projected to use 12.5% of Taiwan's entire electricity supply by 2025. TSMC moved its 100% renewable energy target from 2050 to 2040 under NGO pressure, but in 2024 only 20% of company-wide electricity came from renewables (vs. a 60% 2030 target). Overseas subsidiaries use 100% renewable energy, but Taiwan fabs remain heavily fossil-dependent. TSMC targets doubling energy efficiency within 5 years of volume production for each node; 5nm achieved 0.6x improvement by year 5.
Chemicals and safety: Fabs work with toxic, corrosive, and pyrophoric gases including silane (SiH₄), arsine, phosphine, hydrogen sulfide, ammonia, nitrogen trifluoride (NF₃), chlorine, fluorine, sulfur hexafluoride (SF₆), boron trifluoride, and tungsten hexafluoride. New fabs use totally enclosed processes, automation, and chemical delivery systems to create a barrier between workers and the process, with secondary and tertiary redundancy. PFAS-containing wet chemistries are critical for wet processing but face increasing regulation. Bulk chemical delivery systems (BCDS) typically achieve payback in less than 1.5 years by minimizing handling hazards.
Why It Matters
Environmental constraints are now binding. Water scarcity in Arizona, Texas, and Taiwan is already deciding where fabs get built and how large they can grow. ESG compliance standards are driving companies toward water reclamation and conservation measures. The TSMC Arizona power paradox exemplifies the tension: Phase 1 at 200 MW is manageable, but 1 GW+ expansion rivals a nuclear reactor and requires transmission system expansion that Arizona Public Service must deliver.
What Constrains It
- Water scarcity: Fabs competing for water in drought-prone regions; groundwater depletion concerns
- Grid capacity: 1 GW+ per gigafab requires massive utility infrastructure investment
- PFAS regulation: Critical wet chemistries face increasing environmental scrutiny
- Renewable energy gap: TSMC at 20% RE vs. 60% target; Taiwan's grid remains fossil-heavy
- EHS compliance: "The electric, water, and wastewater requirements can rival that of a moderately-sized town, and the rise of more comprehensive and rigorous ESG compliance standards" are reshaping fab operations
Connects To
Site (environmental factors determine siting suitability); Utilities (water recycling and power sourcing are core environmental functions); Subfab & Vacuum (abatement systems manage emissions); Tools (chemical delivery safety and PFAS regulation affect process chemistries).
Related readingRead how resource pressure changes fab operations.
MOVEMENT
What It Is
The Automated Material Handling System (AMHS) is the circulatory system of the fab. Wafers travel inside FOUPs (Front Opening Unified Pods), sealed containers that maintain cleanroom-class environments for the wafers inside. A fully loaded FOUP weighs 8-15 kg, making manual handling impractical.
The global semiconductor AMHS market was valued at approximately $3.1-3.5 billion in 2024, projected to reach $6.2-6.8 billion by 2033-2034 at 7-8% CAGR. The market is a duopoly: Murata Machinery (48.3% share) and Daifuku (39.4%) together control 87.7% of the global AMHS market. SEMES (Samsung subsidiary) is the largest Korean supplier, with $3.34 billion in AMHS revenue in 2023.
OHT (Overhead Hoist Transport) is the primary transport solution in 300mm wafer fabs, accounting for 38% of the AMHS market. It operates on overhead rails without occupying floor space. OHT systems travel at up to 320 m/min with forking time of approximately 2 seconds, maintaining Class 100 (Class 10 with velocity control) cleanliness.
Key AMHS components include: OHT transport vehicles, FOUP Stocker (high-density storage), Reticle Stocker (for photomasks), Near Tool Buffer (NTB), Overhead Buffer Purge (OHBP), Tower Stocker, Loadport Station, and Tool Loadport Purge (TLP).
The MCS (Material Control System) is the central software that interfaces with MES, RTD, and EAP systems, implementing SEMI standards (SECS, GEM, Stocker-SEM, IB-SEM). Asia-Pacific represents approximately 74% of global AMHS demand, North America approximately 16%.
Why It Matters
In a leading-edge fab, a single wafer may visit 50+ tools and undergo 1,000+ process steps. The AMHS must move FOUPs between tools, to metrology stations, through stockers, and back, without contamination, without dropping, and without introducing particles. Any AMHS failure halts the entire production line. The duopoly structure means that any disruption at Murata or Daifuku affects virtually every 300mm fab on Earth.
What Constrains It
- Duopoly risk: Murata + Daifuku at 87.7% market share; limited alternatives
- Speed vs. cleanliness: Faster OHT movement risks particle generation; velocity-controlled systems add complexity
- Footprint: OHT rails consume overhead space that competes with utility routing and cleanroom airflow
- Software integration: MCS must interface with MES, RTD, and EAP; any software bug can halt wafer flow
- Chinese entrants emerging: Meet Future Technology and Sineva are developing domestic AMHS but limited to Chinese fabs for now
Connects To
Tools (every tool has a loadport; AMHS must interface with lithography, deposition, etch, and metrology); Utilities (OHT rails route through cleanroom airspace); Exit (AMHS routes wafers to probe test and advanced packaging areas); Site (building structure must support OHT rail loads).
Related readingSee why wafer movement is the fab's circulatory system.
EXIT: TEST & PACKAGE
What It Is
Exit is where the wafer becomes a product. The flow proceeds through: wafer sort (probe test), dicing, packaging (for advanced nodes: CoWoS, InFO, SoIC), burn-in, and final test.
Wafer Sort (Probe Test): Every die on a completed wafer is electrically tested before dicing. Defective dies are marked; functional dies are binned by performance. Output is a wafer map. A modern 300mm wafer with thousands of dies is sorted in one to several hours depending on die count, test complexity, and parallelism.
The ATE (Automated Test Equipment) market is an Advantest-Teradyne duopoly. Probe card supply is a tightening three-vendor oligopoly. The economics of test are changing dramatically with advanced packaging: "A $30,000 CoWoS package built on one failed die is a catastrophic yield event." Known-Good-Die (KGD) testing is now critical, packaging a bad die costs 10x-100x more than catching it at wafer probe. A single bad die in a multi-die module (e.g., an AI accelerator with 8 HBM stacks) scraps the entire module.
Advanced Packaging: CoWoS (Chip on Wafer on Substrate) enables 2.5D integration with HBM stacks. InFO (Integrated Fan-Out) enables high-density packaging without a substrate. TSMC-SoIC enables true 3D chip stacking. These packaging technologies are now performance bottlenecks: the AI chip shortage is fundamentally a CoWoS capacity shortage.
Burn-in and Final Test: Burn-in testing powers ICs at elevated temperature to stress products and detect early failures. Wafer-level burn-in subjects devices to testing while still in wafer form. Die cracks at dicing can propagate during assembly and thermal cycles; singulated die testing with active thermal control is being developed for AI/HPC devices. Final test (post-packaging) includes electrical and functional testing, environmental stress testing, sorting and grading, and final inspection before shipment.
Why It Matters
Exit is where all the investment either pays off or doesn't. A fab can have perfect lithography, flawless deposition, and zero etch defects, but if the test program misses a marginal die that fails in a $30,000 CoWoS package, the economics collapse. Advanced packaging (CoWoS, Foveros, 3D IC) is transforming wafer sort from a simple go/no-go gate into a sophisticated known-good-die qualification process. Test time per wafer is growing; probe card supply is tightening.
What Constrains It
- ATE duopoly: Advantest and Teradyne control the market; limited competition
- Probe card supply: Three-vendor oligopoly tightening as test complexity increases
- KGD economics: CoWoS makes die failure catastrophically expensive; test coverage requirements are increasing
- Packaging bottleneck: CoWoS capacity is the binding constraint on AI chip supply; packaging is now the tail that wags the dog
- Dicing reliability: Die cracks propagate; new singulated die testing with active thermal control adds process steps
Connects To
Metrology (test data validates metrology predictions); Movement (AMHS routes wafers to probe stations); Tools (packaging requires lithography, deposition, and etch tools of its own); Site (packaging cleanrooms may be co-located or separate).